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Chapter 3 Timing Diagrams
653X User Manual 3-10 ni.com
Figure 3-7. Burst Input Timing Diagram (PCLK Reversed)
Parameter Description Minimum Maximum
Input Parameters
t
pc
PCLK cycle time
50 —
t
pw
PCLK high pulse duration
20 —
t
pl
PCLK low pulse duration
20 —
t
rs
Setup time from REQ valid to PCLK falling
edge
1 —
t
rh
Hold time from PCLK to REQ invalid
0 —
t
dis
Setup time from input data valid to PCLK
falling edge
0 —
t
dih
Hold time from PCLK to input data valid
0 —
Output Parameters
t
pa
PCLK to ACK valid
— 22
t
ah
Hold time from PCLK to ACK invalid
3 —
All timing values are in nanoseconds.
PCLK
ACK
Data In Valid
REQ
t
dis
t
dih
t
rs
t
pa
t
pw
t
pl
t
pc
t
rh
t
ah