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Chapter 3 Timing Diagrams
© National Instruments Corporation 3-23 653X User Manual
Figure 3-19.
Level ACK Output Timing Diagram
Note
With REQ edge latching disabled (default), output data valid will hold t
rdo
ns after
the REQ edge is asserted. With REQ edge latching enabled, that data will be held for at
most t
rdo
ns after the REQ edge deasserts.
Parameter Description Minimum Maximum
Input Parameters
t
rr*
REQ pulse width 75 —
t
r*r
REQ inactive duration 75 —
t
ar
ACK to next REQ 0 —
Output Parameters
t
aa*
ACK pulse width 225 —
t
ra*
REQ to ACK inactive 100 200
t
r*do
REQ inactive to new output data
(with REQ-edge latching)
050
t
rdo
REQ to new output data
(with REQ-edge latching disabled)
0—
t
doa
Output data valid to ACK
(with REQ-edge latching disabled)
25
1
—
1
t
doa
(min.) = 25 +programmable delay
REQ
Output Data Valid
(REQ-edge
latching)
Output Data Valid
(REQ-edge
latching disabled)
t
r*r
t
r*do
t
ra*
t
doa
t
ar
t
aa*
t
rr*
ACK
t
rdo
ACK and REQ are shown as active high