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Chapter 3 Timing Diagrams
653X User Manual 3-8 ni.com
Figure 3-5. Burst Input Timing Diagram (Default)
Parameter Description Minimum Maximum
Input Parameters
t
rs
Setup time from REQ valid to PCLK 12 —
t
rh
Hold time from PCLK to REQ invalid 0 —
t
dis
Setup time from input data valid to PCLK 4 —
t
dih
Hold time from PCLK to input data invalid 6 —
Output Parameters
t
pc
PCLK cycle time 50 700
1
t
pw
PCLK high pulse duration t
pc
/2 – 5t
pc
/2 + 5
t
pa
PCLK to ACK valid — 18
t
ah
Hold time from PCLK to ACK invalid 3 —
1
t
pc
= programmable delay from 100 to 700 ns, or 50 ns if programmable delay is 0. Timebase stability for the onboard
20 MHz clock source is 100 ppm.
All timing values are in nanoseconds.
PCLK
ACK
Data In Valid
REQ
t
dis
t
dih
t
rs
t
pa
t
pw
t
pc
t
rh
t
ah