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PCI-6110E/6111E User Manual I-2
©
National Instruments Corporation
below-low-level analog triggering mode
(figure), 3-7
block diagrams
PCI-6110E, 3-6
PCI-6111E, 3-7
high-hysteresis analog triggering mode
(figure), 3-9
inside-region analog triggering mode
(figure), 3-8
low-hysteresis analog triggering mode
(figure), 3-9
specifications, A-8
AOGND signal
analog output signal connections, 4-13
description (table), 4-3
signal summary (table), 4-6
B
bipolar input, 3-3
block diagrams
PCI-6110E, 3-1
PCI-6111E, 3-2
board configuration, 2-2
bulletin board support, D-1
bus interface specifications, A-9
C
cables. See also I/O connectors.
custom cabling, 1-5 to 1-6
field wiring considerations, 4-35 to 4-36
optional equipment, 1-5
calibration, 5-1 to 5-3
external calibration, 5-2 to 5-3
loading calibration constants, 5-1 to 5-2
self-calibration, 5-2
clocks, board and RTSI, 3-12
commonly asked questions. See questions and
answers.
common-mode signal rejection, 4-12
ComponentWorks software, 1-3
configuration
PCI-6110E/6111E, 2-2
questions about, C-2
connectors. See I/O connectors.
CONVERT* signal
input timing (figure), 4-24
multiplexer for controlling (figure), 3-11
output timing (figure), 4-24
signal routing, 3-11 to 12
timing connections, 4-23 to 4-25
counter/timer applications, C-4 to C-5
customer communication, xiv, D-1toD-2
D
DAC0OUT signal
analog output signal connections, 4-13
description (table), 4-3
signal summary (table), 4-6
DAC1OUT signal
analog output signal connections, 4-13
description (table), 4-3
signal summary (table), 4-6
DAQ timing connections, 4-17 to 4-26
AIGATE signal, 4-25
CONVERT* signal, 4-23 to 4-25
EXTSTROBE* signal, 4-18 to 4-19
SCANCLK signal, 4-18
SISOURCE signal, 4-25 to 4-26
STARTSCAN signal, 4-22 to 4-23
TRIG1 signal, 4-19 to 4-20
TRIG2 signal, 4-20 to 4-21
typical posttriggered acquisition
(figure), 4-17
typical pretriggered acquisition
(figure), 4-18
DAQ-STC system timing controller
overview, 1-1
questions about, C-1, C-3 to C-4
PCI_E.book Page 2 Thursday, June 25, 1998 12:55 PM