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Appendix A Specifications
PCI-6110E/6111E User Manual A-8
©
National Instruments Corporation
Data transfers ..................................... DMA, interrupts,
programmed I/O
DMA modes....................................... Scatter-gather
Triggers
Analog Trigger
Source
PCI-6110E................................... All analog input channels,
external trigger (PFI0/TRIG1)
PCI-6111E................................... All analog input channels,
external trigger (PFI0/TRIG1)
Level.................................................. ± full-scale, internal;
±10 V, external
Slope.................................................. Positive or negative
(software selectable)
Resolution.......................................... 8 bits, 1 in 256
Hysteresis........................................... Programmable
Bandwidth ......................................... (–3 dB) 5 MHz internal/external
External input (PFI0/TRIG1)
Impedance ................................... 10 kΩ
Coupling...................................... AC/DC
Protection .................................... –0.5 V to (V
cc
+ 0.5) V when
configured as a digital signal,
±35 V when configured as an
analog trigger signal or
disabled, ±35 V powered off
Digital Trigger
Compatibility ..................................... TTL
Response............................................ Rising or falling edge
Pulse width......................................... 10 ns min
PCI_E.book Page 8 Thursday, June 25, 1998 12:55 PM