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PCI-6110E/6111E User Manual I-8
©
National Instruments Corporation
typical posttriggered acquisition
(figure), 4-17
typical pretriggered acquisition
(figure), 4-18
general-purpose timing signal
connections, 4-29 to 4-35
FREQ_OUT signal, 4-35
GPCTR0_GATE signal, 4-30 to 4-31
GPCTR0_OUT signal, 4-31
GPCTR0_SOURCE signal,
4-29 to 4-30
GPCTR0_UP_DOWN signal, 4-31
GPCTR1_GATE signal, 4-32 to 4-33
GPCTR1_OUT signal, 4-33
GPCTR1_SOURCE signal, 4-32
GPCTR1_UP_DOWN signal,
4-34 to 4-35
programmable function input
connections, 4-16 to 4-17
questions about, C-3 to C-5
timing I/O connections (figure), 4-16
waveform generation timing connections,
4-26 to 4-29
UISOURCE signal, 4-28 to 4-29
UPDATE* signal, 4-27 to 4-28
WFTRIG signal, 4-26 to 4-27
timing I/O specifications, A-7 to A-8
timing signal routing, 3-11 to 3-13
board and RTSI clocks, 3-12
CONVERT* signal routing (figure), 3-11
programmable function inputs, 3-12
RTSI triggers, 3-13
transfer characteristic specifications
analog input, A-2 to A-3
analog output, A-5
TRIG1 signal
input timing (figure), 4-20
output timing (figure), 4-20
timing connections, 4-19 to 4-20
TRIG2 signal
input timing (figure), 4-21
output timing (figure), 4-21
timing connections, 4-20 to 4-21
trigger, analog
above-high-level analog triggering mode
(figure), 3-8
avoiding false triggering (note), 3-6
below-low-level analog triggering mode
(figure), 3-7
block diagrams
PCI-6110E, 3-6
PCI-6111E, 3-7
high-hysteresis analog triggering mode
(figure), 3-9
inside-region analog triggering mode
(figure), 3-8
low-hysteresis analog triggering mode
(figure), 3-9
specifications, A-8
triggers
questions about, C-3
specifications
analog trigger, A-8
digital trigger, A-8
U
UISOURCE signal, 4-28 to 4-29
unpacking PCI-6110E/6111E, 1-6
UPDATE* signal
input signal timing (figure), 4-28
output signal timing (figure), 4-28
timing connections, 4-27 to 4-28
V
VCC signal (table), 4-6
VirtualBench software, 1-3
voltage output specifications, A-5 to A-6
PCI_E.book Page 8 Thursday, June 25, 1998 12:55 PM