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Appendix C Common Questions
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National Instruments Corporation C-5 PCI-6110E/6111E User Manual
connector, route external signals to internal timing sources, or tie
internal timing signals together.
If you are using NI-DAQ with LabVIEW and you want to connect
external signal sources to the PFI lines, you can use AI Clock Config,
AI Trigger Config, AO Clock Config, AO Trigger and Gate Config,
CTR Mode Config, and CTR Pulse Config advanced level VIs to
indicate which function the connected signal will serve. Use the Route
Signal VI to enable the PFI lines to output internal signals.
Caution: If you enable a PFI line for output, do not connect any external signal
source to it; if you do, you can damage the board, the computer, and the
connected equipment.
What are the power-on states of the PFI and DIO lines on the I/O
connector?
At system power-on and reset, both the PFI and DIO lines are set to high
impedance by the hardware. This means that the board circuitry is not
actively driving the output either high or low. However, these lines may
have pull-up or pull-down resistors connected to them as shown in
Table 4-2. These resistors weakly pull the output to either a logic high
or logic low state. For example, DIO(0) will be in the high impedance
state after power on, and Table 4-2 shows that there is a 50 kΩ pull-up
resistor. This pull-up resistor will set the DIO(0) pin to a logic high
when the output is in a high impedance state.
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PCI_E.book Page 5 Thursday, June 25, 1998 12:55 PM