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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
Revision 1.0 (08-14-08) 10 SMSC AN 9.6
APPLICATION NOTE
3.5.6 NRDYRTN
Ready Return is an input signal generated by the host controller to establish a handshake signal to
inform the LAN91C111 that the cycle has ended. For LCLK speeds up to 33Mhz, nRDYRTN is typically
asserted in the same LCLK cycle as nSRDY is asserted. For higher LCLK speed, nRDYRTN may trail
nSRDY by one LCLK cycle due to signal resynchronization.
In Non-VL-Bus mode, Ready Return is an input signal generated by the host controller to indicate that
the cycle is not completed and that the next cycle needs to be delayed. nRDYRTN is used to insert
wait states during burst operations. A wait state will be inserted if nRDYRTN is asserted and
subsequently for each clock period that nRDYRTN is held. nRDYRTN is sampled on the falling edge
of LCLK and will insert a wait state on each subsequent falling edge of LCLK that nRDYRTN is held.
3.5.7 NSRDY
nSRDY is an output signal from the LAN91C111 to inform the CPU that it has completed the data
transfer and the CPU can terminate the current active bus cycle. When the bus controller detects the
nSRDY asserted, it may immediately assert nRDYRTN or, at speed greater than 33Mhz, it may
resynchronize nSRDY and assert nRDYRTN on the next LCLK cycle. If the current transfer is a read,
the LAN91C111 holds the read data on the data bus until the LCLK which nRDYRTN is sampled
asserted. nSRDY is asserted low for one LCLK period.
3.5.8 LCLK – Clock Input
LCLK is the system bus clock required for synchronous operation. The clock is input on the LCLK pin
and can be a maximum of 50MHz in operation. The duty cycle of the clock should be 50/50 with the
least amount of jitter as possible well. Typically the clock will be the same clock used on the
microprocessor or microcontroller of the design. The LCLK pin is 5V tolerant. All timings specified in
synchronous or VL-Bus will be in respect to the LCLK. This pin should be tied high or clocked if the
LAN91C111 operates in Asynchronous mode.
3.5.9 Reset
RESET causes the LAN91C111 to go to its default states. RESET must be held for 100nS in order to
force the LAN91C111 into it’s reset state. This is to avoid potential problems with glitches. Once the
100nS-time parameter has been met, the device will remain in reset as long as RESET is held high.
3.5.10 NBE0-NBE3
Byte Enable lines 0 through 3 indicate what type of transfer is occurring, byte, word, or double word.
The LAN91C111 does support all modes of operation. Below is a chart of how transfers are decoded
using the Byte Enable lines:
NBE0 NBE1 NBE2 NBE3
0 0 0 0 Double word access
0 0 1 1 Low word access
1 1 0 0 High word access
0 1 1 1 Byte 0 access
1 0 1 1 Btye 1 access
1 1 0 1 Btye 2 access
1 1 1 0 Byte 3 access