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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
Revision 1.0 (08-14-08) 54 SMSC AN 9.6
APPLICATION NOTE
9.10 MMU Test
The MMU test is broken down into a series of tests that check each command of the MMU.
1. ALLOCATE MEMORY FOR TX
Loop for I = 0 to 3
Write 0x0020 to the MMUCOM register (bank 2, offset 0)
Poll for Alloc INT
Read the INTERRUPT register (bank 2, offset C) until bit 3 (ALLOC INT) is set
Read packet # from ALLOCATION RESULT register
Read (bank 2, offset 3)
Packet # should = I
Read the MEMORY INFORMATION register (MIR)
Read (bank 0, offset 8)
MIR should = 0x0Z04, where Z = 4 – (I+1)
End loop I
Test fails if allocation fails, packet # does not equal I, or MIR register is incorrect.
2. RESET MMU TO INITIAL STATE
Perform step 1 (Allocate memory for TX)
Write 0x0040 to the MMUCOM register (bank 2, offset 0)
Read the MIR register (bank 0, offset 8), should equal 0x0404
Read the FIFO PORTS register (bank 2, offset 4), should equal 8080
Test fails if the MIR or FIFO registers are incorrect.
3. REMOVE FRAME FROM TOP OF RX FIFO
Perform Section 9.7 - EPH Loopback Test, page 62 a total of 2 times
The FIFO register (bank 2, offset 4) should now equal 0x0100
The MIR register (bank 0, offset 8) should now equal 0x0004
Write a 0x0060 to the MMUCOM register (bank 2, offset 0)
The FIFO register should equal 0x0300
The MIR register should equal 0x0004
Write a 0x0060 to the MMUCOM register
The FIFO register should equal 0x8300
The MIR register should equal 0x0004
The test fails if the EPH Loopback fails or the MIR or FIFO registers are incorrect.
4. REMOVE AND RELEASE TOP OF RX FIFO
Perform Section 9.7 - EPH Loopback Test, page 61 a total of 2 times
The FIFO register (bank 2, offset 4) should now equal 0x0100
The MIR register (bank 0, offset 8) should now equal 0x0004