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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
Revision 1.0 (08-14-08) 20 SMSC AN 9.6
APPLICATION NOTE
As you can see by the timing diagram and subsequent timing parameter table the nDATACS signal is
used to indicate that the cycle is a burst mode direct operation. As long as nDATACS remains asserted
the LAN91C111 will continue to read data from the FIFO’s using the Auto-Increment feature. Each
packet of data is available for the host on the rising edge of LCLK and will remain on the bus for a
minimum of 5nS. In read operations, nCYCLE needs to remain high for burst mode operations.
In the above timing diagram nRDYRTN again is used to insert a wait state. In this example a wait is
inserted between the first and second data packet. Again nRDYRTN is sampled on the falling edge of
LCLK and is required to be asserted 10nS prior to this falling edge and remain asserted for 10nS after
the falling edge. As long as nRDYRTN remains asserted wait states will be inserted into the cycle. In
the example above a single LCLK cycle is inserted.
The timing parameter states that the data is available a minimum of 5nS before the rising edge of
LCLK and held a maximum of 15nS after this rising edge. This gives the hold time for the data to be
available from the LAN91C111.
3.12 LAN91C111 Bus Interface
The Bus Interface Unit on the LAN91C111 is flexible and configurable to support multiple types of
processor architectures and configurations. A designer has the choice of either synchronous or
asynchronous and can support burst or non-burst modes of operations. The ability to change
configuration types to accommodate different configurations for different modes of operations is flexible
enough handle different modes of operations dependent upon what needs to be done. For example,
a standard asynchronous transfer can be done to configure the LAN91C111 and then the interface
switched into burst mode using the nDATACS pin to fill the transmit buffer or empty the receive buffer.
This kind of flexibility allows the LAN91C111 to be configured for any number of processor families or
architectures that you may need.
The following pins are used in asynchronous operations:
The following pins are used in synchronous modes of operations:
t15 nRDYRTN Hold after LCLK Falling 10 ns
t17 W/nR Setup to LCLK Falling 15 ns
t17A W/nr Hold After LCLK Falling 3 ns
t19 Data Delay from LCLK Rising (Read) 5 15 ns
SIGNAL NAME BRIEF DESCRIPTION
nADS Address Qualifier
nRD Read operation, active low
nWR Write operation, active low
OPTIONAL SIGNALS
nDATACS Direct access 32-bit mode operation
PARAMETER
MIN TYP MAX UNITS