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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
SMSC AN 9.6 13 Revision 1.0 (08-14-08)
APPLICATION NOTE
accomplished through external circuitry. Signal W/nR has to be asserted high no later than nCYCLE
assertion.
3.6.2 Write Cycle Data Phase - Cycle End
During next rising edge after de-assertion of nCYCLE, write data has to be presented to the
LAN91C111. The data bus will need to be stable at least 15nS prior to the rising edge of LCLK and
are required to hold 4nS, as specified by timing parameter t18 and t20. nSRDY (translated to nLRDY
for the VL-Bus) is asserted during data latching for one cycle. Data input latch is transparent during
nSRDY is low, data is being written to internal registers. nSRDY will de-assert indicating that the data
was written to the LAN91C111 successfully. The W/nR signal can be released 3nS after the rising edge
of LCLK during the data phase of the cycle.
3.6.3 Read Cycle
We will now examine a Read Cycle using the VL-Bus on the LAN91C111. Below is the timing diagram
and parameter listing from the Data Sheet. As you can see the Read cycle requires one more clock
cycle than the Write cycle. This extra time is required for the LAN91C111 to fetch the data internally
prior to presenting it on the Data Bus.
Figure 3.5 Synchronous Read Cycle - NVLBUS=0
PARAMETER MIN TYP MAX UNITS
t8 A1-A15, AEN, nBE [3:0] Setup to
nADS Rising
8ns
t9 A1-A15, AEN, nBE[3:0] Hold After
nADS Rising
5ns
t10 nCYCLE Setup to LCLK Rising 5 ns
t21t21
t11
t8
t9
t16
t23
t24
t20
t10
Valid
Valid
Clock
Address, AEN, nBE[3:0]
nADS
W/nR
nCYCLE
Read Data
nSRDY
nRDYRTN