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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
SMSC AN 9.6 17 Revision 1.0 (08-14-08)
APPLICATION NOTE
Figure 3.8 Asynchronous Cycle - nADS=0
(nDATACS Used to Select Data Register; Must Be 32 Bit Access)
This timing diagram and subsequent parameter information detail a typical reads or write operation.
As you can see by the timing diagram the first step is to have the address qualified with the assertion
of nADS. Since this discussion is focused on the use of the nDATACS signal, this step is accomplished
by programming the pointer register to where the access is going to occur. By using nDATACS the
values on the address bus and the byte enable lines (BE0-BE3) are ignored.
There is a minimum delay of 2nS prior to the assertion of nRD or nWR. For a read operation the data
becomes valid on the data bus a maximum of 30nS after the assertion of the nRD line. For a write
operation the data needs to be valid for a minimum of 10nS prior to the de-assertion of nWR and needs
to be held for 5nS after this de-assertion.
In asynchronous mode of operation, to accomplish multiple back-to-back transfers (either nWR or nRD)
the minimum time between transactions is 80nS. This means that you can pulse either nWR or nRD
at 80nS intervals. In the case of full duplex mode the timing changes to 100nS between pulses.
3.9 Burst Mode Operation Timing – Synchronous Operation
Burst mode operations using the LAN91C111 require that the nVLBUS pin to be de-asserted and that
an LCLK be provided. The nCYCLE pin is used to indicate that bursting is to be done and the
PARAMETER MIN TYP MAX UNITS
t1 nDATACS Setup to nRD, nWR
Active
2ns
t2 nDATACS Hold After nRD, nWR
Inactive (Assuming nADS Tied
Low)
5ns
t3A nRD Low to Valid Data 30 ns
t4 nRD High to Data Invalid 2 15 ns
t5 Data Setup to nWR Inactive 10 ns
t5A Data Hold After nWR Inactive 5 ns
t6A nRD Strobe Width 30 ns
t5A
t5t1
t4t3A
t2
t6At6A
D0-D31 Valid
Valid
nDATACS
Read Data
nRD, nWR
Write Data