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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
SMSC AN 9.6 27 Revision 1.0 (08-14-08)
APPLICATION NOTE
In an ISA like application, system designers can have the choices of always using the chip at 300h,
or having the controlling software access the base address registers at 300h and change it to other
I/O address after accessing the chip at that address. Similarly for the other values usually stored in
the EEPROM, the driver will have to load them at software initialization. For the case of the node
address, given that it is unique and different for each system, it will have to be stored in some other
external storage place and will be loaded by the driver or firmware at initialization time.
4.4.3 How to Change the IOBASE Address
The default IOBASE Address of the LAN91C111 is 0x0300h. If the system designers try to design one
of the LAN9000 chips in the system, where some other device already has taken the IOBASE address
300, they may first disable or unplug that device, then install the LAN91C111 into the system using the
default IOBASE address 300. Once everything setup properly, they can change the Ethernet IOBASE
address to other values by writing to BASE ADDRESS Register with different and available IOBASE
address, then store these values to the serial EEPROM by writing 1 to the STORE bit in the CONTROL
Register. After all these steps completed successfully, the system designer may power-down the
system and re-enable the device that was originally assigned to IOBASE address 300. The
LAN91C111 will load the proper IOBASE address from the serial EEPROM at power up.
4.5 Power Supply Decoupling
The analog power plane AVDD and the digital power plane are recommended to be separated to
eliminate noise. All the V
DD
pins should be connected together as closely as possible to the device
with a large V
DD
plane. If the V
DD
pins vary in potential by even a small amount, noise and latch up
can result. The V
DD
pins should be kept to within 50MV of each other.
All the GND pins should also be connected together as closely as possible to the device with a large
ground plane. If the GND pins vary in potential by even a small amount, noise and latch up can result.
The GND pins should be kept to within 50MV of each other. A 0.01–0.1 mF decoupling capacitor
should be connected between each V
DD
/GND set as closely as possible to the device pins, preferably
within 0.5 inches. The value should be chosen based on whether the noise from V
DD
-GND is high or
low frequency. This will need to be determined on a design basis.
The V
DD
connection to the transmit transformer center tap has to be well decoupled to minimize
common mode noise injection from the supply into the twisted-pair cable. It is recommended that a
0.01 mF decoupling capacitor is placed between the center-tap V
DD
and the GND plane. This
decoupling capacitor should be physically placed as close as possible to the transformer center tap,
preferably within 0.5".
The PCB layout and power supply decoupling discussed above should provide sufficient decoupling to
achieve the following when measured at the device:
AC noise voltage measured across each V
DD
/GND set should be less than 100mVp-p
All V
DD
pins should be within 50mVp-p of each other
All GND pins should be within 50mVp-p of each other.
Noise considerations need to be analyzed on a design-by-design basis. The measurements provided
above are only recommendations and standard engineering practices need to be adhered too in order
to have a reliably functional system.
4.6 System Power Consumption
With internal PHY enabled, the typical power supply current drawn by all V
DD
pins of the LAN91C111
is about 100mA, and the additional power supply current drawn by the external magnetic circuitry of
SMSC’s reference design is about 100mA. Using SMSC’s reference design the Ethernet solution
draws a total of about 200mA current. When the internal PHY enters powerdown mode, the total
Ethernet system drops to about 15mA.