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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
SMSC AN 9.6 57 Revision 1.0 (08-14-08)
APPLICATION NOTE
10.2 New Features and Modification
The BIU of the LAN91C111 remains the same as the original Feast (LAN91C100FD). It can handle
both synchronous and asynchronous transfers. The cycle types can be mixed as long as they are not
active simultaneously.
10.2.1 Receive/PHY Control Register
The Memory Configuration Register of the LAN91C100FD has been eliminated and the address used
for a new Receive/PHY Control Register in the LAN91C111. The Memory Reserved for Transmit
function was formerly used to allow the host CPU to reserve memory to be used later for transmits,
thereby limiting the amount of memory available for received packets. The 91C111 dynamically
allocates its internal 8K memory between transmitted and received packets. The Memory Reserved for
Transmit function in Memory Configuration Register is no longer defined in LAN91C111.
The new Receive/PHY Control Register has been added to control the internal PHY. It contains the
following bits: SPEED, DPLX, ANEG, and LED’s select bits.
SPEED
Speed selects Input. This bit selects 10/100 PHY operation when the ANEG Bit = 0. When the ANEG
bit = 1, this bit is ignored and 10/100 operation is determined by the PHY control register 0.13 or the
outcome of the Auto-negotiation. When this bit is set (1), the Internal PHY will operate at 100Mbps.
When this bit is cleared (0), the Internal PHY will operate at 10Mbps.
DPLX
Duplex Select - This bit selects Full/Half Duplex operation. This bit is valid only when the ANEG Bit,
defined in this section is cleared (0). When ANEG is set (1), this bit has no effect. When this bit is set
(1), the PHY is placed in Full Duplex Mode. When this bit is cleared (0), the PHY is placed in Half
Duplex mode.
ANEG
Auto-negotiation mode select - When this bit is set (1), the PHY is placed in Auto-negotiation mode.
When this bit is cleared (0), the PHY is placed in manual mode and 10/100 and the SPEED and
nDPLX bits determine Half/Full Duplex respectively. Default 0. For more information about
AutoNegotiation algorithm, please see datasheet section 5.7.12.
Note: that, setting these bits (SPEED, DPLX and ANEG) can override the bits (SPEED, DPLX and
ANEG_EN) in the internal PHY MI Control Register.
LED
LED’s function select - The LS[0-2]A and LS[0-2]B bit define what LED control signals are routed to
the nLED
A
and nLED
B
output pins. Please see the LED selection table for detail.
10.2.2 Memory Information Register
In the LAN91C111, MEMORY SIZE in the Memory Information Register has the default value of 4 as
required for the internal 8K SRAM.
10.2.3 RX_OVRN bit
In the LAN91C100, RX_OVRN bit in the EPH Status register is set high (1) when a memory allocation
in the external SRAM buffer fails upon receipt of a frame. Because of the receive allocation failure,
FIFO entries for the current frame are discarded. The receiver remains enabled and will receive
subsequent frames if memory is available. In the LAN91C111, this bit is no longer defined and it has
been replaced by RESERVED. The RX_OVRN bit of the Interrupt Status Register serves the same
purpose as the RX_OVRN bit of the EPH Status Register and should be used as an indicator of a
receiver overrun.