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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
SMSC AN 9.6 55 Revision 1.0 (08-14-08)
APPLICATION NOTE
Write a 0x0080 to the MMUCOM register (bank 2, offset 0)
The FIFO register should equal 0x0300
The MIR register should equal 0x0104
Write a 0x0080 to the MMUCOM register
The FIFO register should equal 0x8300
The MIR register should equal 0x0204
The test fails if the EPH Loopback fails or the MIR or FIFO registers are incorrect.
5. RELEASE SPECIFIC PACKET
Loop for I = 0 to 3
Write 0x0020 to the MMUCOM register (bank 2, offset 0)
Poll for Alloc INT
Read the INTERRUPT register (bank 2, offset C) until bit 3 (ALLOC INT) is set
Read packet # from ALLOCATION RESULT register
Read (bank 2, offset 3)
Packet # should = I
Read the MEMORY INFORMATION register (MIR)
Read (bank 0, offset 8)
MIR should = 0x0Z04, where Z = 4 – (I+1)
End loop I
Read the MIR register (bank 0, offset 8), should equal 0x0004
Read the FIFO PORTS register (bank 2, offset 4), should equal 0x8083
Loop for I = 0 to 3
Write the PACKET NUMBER register (bank 2, offset 2) = I
Write 0x00A0 to the MMUCOM register (bank 2, offset 0)
Read the MIR register, should equal 0x0Z04, where Z = I+1
End loop I
The test fails if the allocation fails, or the MIR or FIFO registers are incorrect.
6. ENQUEUE PACKET INTO TX FIFO
Loop for I = 0 to 3
Write 0x0020 to the MMUCOM register (bank 2, offset 0)
Poll for Alloc INT
Read the INTERRUPT register (bank 2, offset C) until bit 3 (ALLOC INT) is set
Read packet # from ALLOCATION RESULT register
Read (bank 2, offset 3)
Packet # should = I
Read the MEMORY INFORMATION register (MIR)
Read (bank 0, offset 8)
MIR should = 0x0Z04, where Z = 4 – (I+1)
End loop I
Turn on the transmitter
Write 0x0001 to the TRANSMIT CONTROL register (bank 0, offset 0)
Loop for I = 0 to 3
Write I to the PACKET NUMBER register (bank 2, offset 2)
Write 0x00C0 to the MMUCOM register