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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
Revision 1.0 (08-14-08) 30 SMSC AN 9.6
APPLICATION NOTE
A power up Auto-Negotiation enable initialization sequence is provided below for your reference:
1. Power up the chip.
2. Wait for 50ms.
3. Reset the chip by setting and clearing the SOFT_RST bit in the Receive Control Register. (Write
0x8000, then write 0x0000)
4. Wait for 50ms.
5. Set the ANEG bit to 1 in the Receive/PHY Control Register (MAC Register, Bank 0, Offset A) to
enable the Auto_Negotiation mode.
6. Reset PHY by set the RST bit of PHY Register 0 (0x8000);
7. Turn off the isolation mode of the internal PHY by writing x1000 to the PHY Register 0 – Control
Register. The PHY will start the Auto_Negotiation Process.
8. The PHY should complete the Auto_Negotiation process within 1.5 second, thus the driver should
wait for 1.5 second, then read the ANEG_ACK bit and the LINK bit in the PHY Register 1 – Status
Register to check whether the Auto_Negotiation Process is completed and Link is established.
Case 1:
1. If Auto_Negotiation Process is completed and it successfully established LINK, the ANEG_ACK bit
and the LINK bit will be read as “1”
2. Read the SPDDET bit and the DPLXDET bit in the PHY Register 18 – Status Output Register to
check the outcome of Auto_Negotiation Process.
3. If the DPLXDET bit is read as “1”, that means that the PHY is placed in Full Duplex mode, the
driver will need to write “1” to the SWFDUP bit in the MAC Register Bank 0 Offset 0 --Transmit
Control Register to enable Full Duplex mode for the MAC. If the DPLXDET bit is read as “0”, that
means that the PHY is placed in Half Duplex mode, the driver will need to write “0” to the SWFDUP
bit in the MAC Register Bank 0 Offset 0 --Transmit Control Register to switch the MAC to Half
Duplex mode
Case 2:
1. If either the ANEG_ACK bit or the LINK bit is read as “0”, you may restart the Auto_Negotiation
Process for X times until the process is completed and successful. The Auto_Negotiation Process
can be restarted by the ANEG_RST bit (Write 0x3200 to PHY Register 0 – Control Register).
2. Wait for 1.5 second, and then follow the steps 1 to 3 indicated in Case 1.
Case 3:
1. If cable is unplugged or disconnected, the PHY enters Link fail state. The LNKFAIL bit in the PHY
Register 18 –Status Output Register is set, but user has to make sure that the appropriate MASK
bits (the MINT bit and the MLNKFAIL bit in PHY Register 19 – MASK Register) are cleared to
enable interrupt. Also, user has to make sure that the MDINT MASK bit in the MAC BANK 2 offset
D – Interrupt MASK Register is set to enable interrupt. Thus whenever the PHY enters Link fail
state, the host or the OS will be notified. Meanwhile Auto_Negotiation Process will restart again,
the driver should wait for 1.5 second, then follow the steps 1 to 3 indicated in Case 1 or Case 2
to complete the Auto_Negotiation Process.
2. Whenever the device enters the Link Fail State (LINK bit is read as “0”) after having had a valid
10Mbps link (indicated by LINK bit=1, ANEG_ACK=1 and SPDDET=0), steps 6 to 8 above should
be applied to complete the auto-negotiation steps.
Case 4:
1. If hardware reset or the PHY reset is performed, user should follow steps 4 to 8 to complete the
auto-negotiation steps.