Filter
Top Products
SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
Revision 1.0 (08-14-08) 50 SMSC AN 9.6
APPLICATION NOTE
8 Reset Operation
The LAN91C111 can be reset by either hardware or software. A hardware reset can be accomplished
by asserting the RESET pin during normal operation, or upon powering up the device. This input is
not considered active unless it is active for at least 100ns to filter narrow glitches.
Both the MAC and the internal PHY are reset if a hardware reset is performed. All registers will be
reset to the default values and the hardware configuration values will be re-latched into the device.
The positive Reset pulse applied to RESET pin must remain asserted with a duration period of at least
100ns.
Software reset can be accomplished by setting the SOFT_RST bit in the MAC Receive Control
Register. Setting the SOFT_RST bit high, and terminated by writing the bit low performs the internal
system reset. Data in the EEPROM is not loaded after software reset. For the internal PHY, writing
1 to RST bit will reset the registers of the internal PHY to default values. This reset bit is a self-clearing
and it returns a value of 1 until the reset process is completed. The internal PHY is guaranteed to be
ready 50ms after the reset is initiated. Software drive should wait for 50ms after setting the RST bit
high prior to access to the internal PHY registers. Writes to the control register bits, other than RST
bit, have no effect until the reset process has been completed.
9 Functional Test and Diagnostic
The section provides routines can be used for functionally testing the 91C111. These tests will exercise
the major blocks of the MAC and PHY.
9.1 MAC Register Test
Checks the I/O registers in 16-bit mode.
Loop for I = 0 to 3 (for banks 0 to 3)
Write the Bank Select Register (offset 0x0E = I) to select current bank
Loop for J = 0 to C, step 2 (for offset 0x00 to 0x0C)
Read the current register (offset J) and store the current data in a temp variable
Write the current register (offset J) with the data pattern
Read the current register (offset J) and compare data bit-by-bit
Restore the saved variable back to the current register
End Loop J
End Loop I
9.2 RAM Buffer Test
Performs a 16-bit write/read on the internal 8K RAM buffer. The ram is accessed through the DATA
register, which is mapped through two FIFO's and is addressed by the POINTER register. The data
values written should be patterns with alternating bit or random values for maximum effectiveness.
Loop for I = 0 to 3 (4 packets of memory @ 2048 bytes per packet)
Allocate packet memory
Write 0x0020 to the MMUCOM register (bank 2, offset 0)
Poll for Alloc INT bit
Read the INTERRUPT register (bank 2, offset C) until bit 3 (ALLOC INT) is set
Read allocated packet number from ALLOCATION RESULT register (bank 2, offset 3)
Write this packet # into the PACKET NUMBER register (bank 2, offset 2)
Loop for J = 0 to 1023 (total of 1024 words of data)