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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
Revision 1.0 (08-14-08) 58 SMSC AN 9.6
APPLICATION NOTE
10.2.4 MDINT Interrupt bit
MDINT bit replaced the RX_DISC INT bit in the Interrupt Status Registers. nRXDISC PIN COUNTER
bits in the RCV Register are also no longer defined, since the nRXDISC pin is removed. The MDINT
bit is set if any of the following bits in the internal PHY MI Serial Port Status Output Register (Register
18) change state.
1. LNKFAIL (link fail detect),
2. LOSSSYNC (de-scramble loss of synchronization detect),
3. CWRD (Invalid 4B5B code detected on receive data),
4. SSD (no start of stream delimiter detected on received data),
5. ESD (no end of stream delimiter detected on receive data),
6. PROL (reverse polarity detected),
7. JAB (jabber detected),
8. SPDDET (Device in 10/100Mbps mode),
9. nDPLXDET (full/half duplex detected).
10.2.5 Internal PHY Registers
The MII cleanly separates the Data Link Layer and Physical Layer. The PHY MI Serial Port Register
controls the internal PHY, and reading or writing the MAC’s Management Interface Register can access
this Register. All the internal PHY register bits in the LAN91C111 remain same as the SMSC
LAN83C183.
10.2.6 Media Independent Interface (MII)
The LAN91C111 supports only the MII interface for connection of external PHY’s. There is no support
for legacy serial transceivers since the pins that offered that support in the LAN91C100FD have been
removed in the LAN91C111. The AUI SELECT bit in LAN91C100FD Configuration Register has been
changed to RESERVED in the LAN91C111. In order for any software to work properly with the
LAN91C111 this RESERVED bit in Configuration Register (bank 1) should always be set to 0. The
LAN91C100FD MII SELECT bit has been changed to the EPH POWER EN bit in the LAN91C111.
(See Power Management.)
10.2.7 Power Management
The LAN91C111 Configuration Register EPH POWER EN bit for power management has replaced
the LAN91C100FD MII SELECT bit . When EPH POWER EN is cleared (0), the Host will place the
EPH in a low power mode. The Ethernet MAC will gate off the 25Mhz TX and RX clock and the MAC
will no longer be able to receive and transmit packets. The Host interfaces however will still be active
allowing the Host to access the LAN91C111 through Standard I/O accesses. All LAN91C111 registers
will still be accessible. Status and control will not be allowed until the EPH POWER EN bit is set and
a RESET MMU command is initiated. For further information about Power Management, please see
section 8.1 of the datasheet -- Software Driver and Hardware Sequence Flow for Power Management.
10.2.8 Internal PHY and External PHY Selection
The LAN91C111 integrates the Physical Layer (PHY). The data path connection between the MAC and
the internal PHY is provided by the internal MII. The internal PHY address is 00000, the driver must
use this address to talk to the internal PHY. The LAN91C111 also supports the EXT_PHY mode for
the use of an external PHY, such as HPNA. This mode isolates the internal PHY to allow interface with
an external PHY through the MII pins. To enter this mode, set the EXT PHY bit to 1 in the Configuration
Register. Otherwise, clear this bit to enable the internal PHY.