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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
Revision 1.0 (08-14-08) 52 SMSC AN 9.6
APPLICATION NOTE
** The packet will now be sent on the wire when the line is clear **
Poll for completion (<= 100ms)
Read the INTERRUPT register until bit 1 (TX INT) is set (bank 2, offset C)
Read the status word of the packet
Write 0x6000 to the POINTER register (TX, RD, AUTOINC), (bank 2, offset 6)
Read the DATA register (bank 2, offset 8) to get the Status Word of the packet
The Status Word will show any errors in transmission; it mirrors the EPH STATUS register (bank 0, offset 2)
9.4 Releasing The Transmitted Packet
Write 0x00A0 to the MMUCOM register (bank 2, offset 0) to release the packet and its associated
memory. Poll the BUSY bit (bit 0) of the MMUCOM register until it is clear to verify the operation is
complete
It is recommended that the transmitted packet be released immediately after updating any statistics,
to free up buffer memory. If the auto release feature is used, the MAC automatically releases the
packet after transmission.
9.5 Receiving A Packet
The following steps show the sequence to receive a packet.
Turn on the receiver
Write 0x0100 in the RCR register (bank 0, offset 4)
Loop on RX INT until a packet is received
Read the INTERRUPT register (bank 2 , offset C) until bit 0 (RCV INT) is set
Read the receive packet
The receive packet # will be at the top of the RX FIFO (bank 2, offset 4, high byte) if no previous
packet was received
Set the POINTER register (bank 2, offset 6) for RCV, RD, AUTOINC
Write 0xE000
Read the DATA register (bank 2, offset 8), successive word reads:
Read the status word
Read the byte count
Read the destination address (bytes 10)
Read the destination address (bytes 32)
Read the destination address (bytes 54)
Read the source address (bytes 10)
Read the source address (bytes 32)
Read the source address (bytes 54)
Read the packet size
Read the control word
9.6 Releasing A Received Packet
Write 0x0080 to the MMUCOM register (bank 2, offset 0). This releases the packet number present in
the RX FIFO register (the last packet received)
It is recommended that the received packet be released immediately after updating any statistics, to
free up buffer memory.