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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
Revision 1.0 (08-14-08) 12 SMSC AN 9.6
APPLICATION NOTE
Figure 3.4 Synchronous Write Cycle - nVLBUS=0
It is important to remember that timings are determined by the LCLK signal since this is a synchronous
bus. If you examine the timing diagram for the write cycle in VL-Bus (Synchronous) mode you should
observe the following:
3.6.1 Write Cycle Address Phase - Cycle Start
The Address Bus, AEN, and the Byte Enable lines (BE0-BE3), as presented by the microprocessor/
microcontroller, should be stable 8nS prior to the de-assertion of nADS. The de-assertion of nADS
latches in the address and transfer size to the LAN91C111. These lines should also be held for a
minimum of 5nS after the de-assertion of nADS to ensure this latching. nLDEV will assert at a minimum
of 30nS after the address has been decoded by the de-assertion of nADS and the LAN91C111 claims
the cycle. The signal nCYCLE is synchronous to LCLK, the generation of nCYCLE will need to be
PARAMETER MIN TYP MAX UNITS
t8 A1-A15, AEN, nBE[3:0] Setup to nADS Rising 8 ns
t9 A1-A15, AEN, nBE[3:0] Hold After nADS Rising 5 ns
t10 nCYCLE Setup to LCLK Rising 5 ns
t11 nCYCLE Hold after LCLK Rising (Non-Burst Mode) 3 ns
t16 W/nR Setup to nCYCLE Active 0 ns
t17A W/nR Hold after LCLK Rising with nSRDY Active 3 ns
t18 Data Setup to LCLK Rising (Write) 15 ns
t20 Data Hold from LCLK Rising (Write) 4 ns
t21 nSRDY Delay from LCLK Rising 7 ns
t21t21
t11
t8
t9
t16
t23
t24
t20
t10
Valid
Valid
Clock
Address, AEN, nBE[3:0]
nADS
W/nR
nCYCLE
Read Data
nSRDY
nRDYRTN