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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
Revision 1.0 (08-14-08) 56 SMSC AN 9.6
APPLICATION NOTE
Poll for TX INT
Read the INTERRUPT register (bank 2, offset C) until bit 1 (TX INT) is set (< 100ms)
End loop I
The test fails if the allocation fails, the MIR register is incorrect, or the TX INT bit was not set for any
packet within 100ms.
7. RESET TX FIFO’s
Perform Section 9.7 - EPH Loopback Test, page 62 one time
Write 0x0020 to the MMUCOM register (bank 2, offset 0)
Poll for Alloc INT
Read the INTERRUPT register (bank 2, offset C) until bit 3 (ALLOC INT) is set
Turn off transmitter
Write 0x0000 to the TRANSMIT CONTROL register (bank 0, offset 0)
Write 0x00C0 to the MMUCOM register
Read the MIR register (bank 0, offset 8), should equal 0x0104
Read the FIFO PORTS register (bank 2, offset 4), should equal 0x0100
Write 0x00E0 to the MMUCOM register
Read the MIR register, should equal 0x0104
Read the FIFO register, should equal 0x0182
The test fails if the EPH loopback fails, the allocation fails, or the MIR or FIFO registers are incorrect.
If any of above tests fails, please check your hardware and software to debug the chip again.
10 Migrating From LAN91C100FD and LAN83C183 to LAN91C111
This section provides guidelines for migrating from SMSC’s discrete MAC+PHY solution
(LAN91C100+LAN83C183) to SMSC’s integrated MAC+PHY solution the LAN91C111. While portions
of this material is repetitive with other sections above, it has been consolidated here to aid design
engineers with the specific task of migrating from an existing LAN91C100FD design to the SMSC
LAN91C111.
10.1 91C111 Overview
The LAN91C111 is a non-PCI 10/100Mbps Ethernet Controller that integrates the Media Access
Control (MAC), the Physical Layer Device (PHY) and an 8K Byte packet buffer SRAM on a single chip.
The MAC includes a dual speed (10/100) CSMA/CD engine and supports both synchronous and
asynchronous buses. SMSC’s patented Memory Management Unit (MMU) dynamically and efficiently
manages buffer memory with minimal host CPU overhead. The PHY contains the functions that
transmit, receive, and manage the encoded signals that are impressed on and recovered from the
physical medium.