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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
Revision 1.0 (08-14-08) 36 SMSC AN 9.6
APPLICATION NOTE
6 Big and Little Endian Issues on the LAN91C111
6.1 Introduction
The LAN91C111 is designed as a Little Endian architecture device. In order to accommodate the use
of this device on Big Endian architectures there needs to be an understanding of these implications.
This application note is intended to discuss the use of the LAN91C111 on Big Endian type architecture
and the requirements that they may pose.
6.2 Definition
What constitutes Big Endian versus Little Endian? The reference to the endian of architecture implies
how this architecture references memory. In the early days of computing most computers (mainframes)
referenced memory with the Most Significant Bit (MSB) being to the left, just as you read, from left to
right. Little Endian on the contrary the MSB is on the right reading from right to left format. While this
may seem insignificant at first, the confusion comes into play when dealing with words and double
words.
6.2.1 Big Endian
In Big Endian format the high bytes of a multi-byte quantity are stored at lower address, and the low
bytes are stored at higher addresses. Motorola’s 68000 families use the Big Endian format. As an
example, in a Big Endian architecture the hexadecimal word 1234h would be stored with it’s MSB
byte value 12h in byte address location 0h, and its LSB byte value 34h stored in byte address location
1h. In a word memory configuration (double byte), the memory value would be 3412h at a word
address of 0h. The hexadecimal double word 12345678h would be stored as 78563412h at a double
word address of 0h.
Table 6.1 Little Endian Memory Images
Double Word Value to be Stored = 12345678h
Motorola 680x0 microprocessors, IBM PowerPC, Hewlett-Packard PA-RISC, and Sun SuperSPARC
processors are Big Endian. A number of Big Endian processors, such as the PowerPC, support Little
Endian devices internally through a technique known as swizzling. These types of processors can be
known as Bi-Endian. Besides the PowerPC, the MIPS processors and DEC Alpha processors support
some subset of Bi-Endian operations. For more information regarding whether or not your processor
of choice supports Little Endian devices, please refer to your processors documentation.
6.2.2 Little Endian
In the Little Endian format the high-bytes of a multiple byte quantity are stored at the higher addresses,
and the low-bytes are stored at lower addresses. Intel’s 80x86 family uses the Little Endian format..
As an example, in a Little Endian architecture, the hexadecimal word 1234h would be stored the LSB
byte value 34h in byte address location 0h, and it’s MSB byte value 12h stored in byte address location
1h. In a word memory configuration (double byte), the memory value would be 1234h at a word
address of 0h. The hexadecimal double word 12345678h would be stored as 12345678h at a double
word address of 0h.
BYTE ADDRESS
32 10
DATA VALUES (H)
78 56 34 12
BINARY VALUES
0001 0010 0011 0100 0101 0110 0111 1000