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VXIMonitor Subsystem
3–156
VX1410A & VX1420A IntelliFrame Mainframe Instruction Manual
3. Query operation register to check if either D5, D8, D9 or D10 are set.
STAT:OPER?
The system response: 288 (0 x 120 – VXI Triggers set and VXI Monitor)
4. Since the VXI Trigger bit was set, now query the Trigger register.
STAT:OPER:VXIT?
The system response: 16 (0 x 10 – TTL4 Trigger occurred).
5. Query the time that TTL Trigger line 4 triggered.
STAT:OPER:VXIT:TRIG? TTL4
The system response: 0,34,30 (Trigger occurred on line TTL4 34.5 minutes
after power on).
6. When the “STAT:OPER?” query was performed, the VXI Monitor bit was
also set. Use the following command to examine specifically what event
occurred.
STAT:OPER:VXIM?
The system response: 3 (BERR and SYSFAIL are set).
7. STAT:OPER:VXIM:BERR?
The system response: A16 (Bus Error occurred in A16 address space).
8. STAT:OPER:VXIM:SYSF?
The system response: 1, 30, 0 (SYSFAIL occurred one and one-half hours
after power-up)
NOTE. If this test were run with the VXI Monitor enable register set to zero
(“STAT:OPER:VXIM:ENABLE 0”), the VXI Monitor bit would not be set in the
operation register. However, if the VXI Monitor enable register was set to 0 x F
(“STAT:OPER:VXIT:ENABLE 15”), then only triggers on TTL0, TTL1, TTL2
and TTL3 lines will cause the VXIT trigger bit to be set in the operation register
(“STAT:OPER?”). The VXI Trigger register (“STAT:OPER:VXIT?”) will always
show all Trigger lines that are triggered, regardless of the setting in the enable
register.