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ARM Instruction Reference
4-14 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
Rm
is a register containing a value to be used as the offset.
The offset syntax is the same for LDR and STR, doublewords on page 4-15.
Address alignment for halfword transfers
The address must be even for halfword transfers.
If your system has a system coprocessor (cp15), you can enable alignment checking.
Non halfword-aligned 16-bit transfers cause an alignment exception if alignment
checking is enabled.
If your system does not have a system coprocessor (cp15), or alignment checking is
disabled:
• a non halfword-aligned 16-bit load corrupts
Rd
• a non halfword-aligned 16-bit save corrupts two bytes at [address] and
[address–1].
Loading to r15
You cannot load halfwords or bytes to r15.
Architectures
These instructions are available in ARM architecture v4 and above.
Examples
LDREQSH r11,[r6] ; (conditionally) loads r11 with a 16-bit halfword
; from the address in r6. Sign extends to 32 bits.
LDRH r1,[r0,#22] ; load r1 with a 16 bit halfword from 22 bytes
; above the address in r0. Zero extend to 32 bits.
STRH r4,[r0,r1]! ; store the least significant halfword from r4
; to two bytes at an address equal to contents(r0)
; plus contents(r1). Write address back into r0.
LDRSB r6,constf ; load a byte located at label constf. Sign extend.
Incorrect example
LDRSB r1,[r6],r3,LSL#4 ; This format is only available for word and
; unsigned byte transfers.