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Vector Floating-point Programming
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 6-29
6.7.10 FMDRR and FMRRD
Transfer contents between two ARM registers and a double-precision floating-point
register.
Syntax
FMDRR{cond} Dn, Rd, Rn
FMRRD{cond} Rd, Rn, Dn
where:
cond
is an optional condition code (see VFP and condition codes on page 6-8).
Dn
is the VFP double-precision register.
Rd, Rn
are ARM registers. Do not use r15.
Usage
FMDRR Dn, Rd, Rn
transfers the contents of
Rd
into the low half of
Dn
, and the contents of
Rn
into the high half of
Dn
.
FMRRD Rd, Rn, Dn
transfers the contents of the low half of
Dn
into
Rd
, and the contents of
the high half of
Dn
into
Rn
.
Exceptions
These instructions do not produce any exceptions.
Architectures
These instructions are available in VFPv2 and above.
Examples
FMDRR d5, r3, r4
FMRRDPL r12, r2, d2