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ARM Instruction Reference
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 4-15
4.2.3 LDR and STR, doublewords
Load two consecutive registers and store two consecutive registers, 64-bit doubleword.
Syntax
These instructions have four possible forms:
• zero offset
• pre-indexed offset
• program-relative
• post-indexed offset.
The syntax of the four forms are, in the same order:
op{cond}D Rd, [Rn]
op{cond}D Rd, [Rn, Offset]{!}
op{cond}D Rd, label
op{cond}D Rd, [Rn], Offset
where:
op
is either
LDR
or
STR
.
cond
is an optional condition code (see Conditional execution on page 4-4).
Rd
is one of the ARM registers to load or save. The other one is
R(d+1)
.
Rd
must be an even numbered register, and not
r14
.
Rn
is the register on which the memory address is based.
Rn
must not be the same as
Rd
or
R(d+1)
, unless the instruction is either:
• zero offset
• pre-indexed without writeback.
Offset
is an offset applied to the value in
Rn
(see Offset syntax on page 4-16).
label
is a program-relative expression. See Register-relative and
program-relative expressions on page 3-23 for more information.
label
must be within ±252 bytes of the current instruction.
!
is an optional suffix. If ! is present, the final address including the offset
is written back into
Rn
.