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5-36 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
5.4.4 BLX
Branch with Link, and optionally exchange instruction set.
Syntax
BLX Rm
BLX label
where:
Rm
is an ARM register containing the address to branch to.
Bit 0 of
Rm
is not used as part of the address. If bit 0 of
Rm
is clear:
• Bit 1 must also be clear.
• The instruction clears the T flag in the CPSR. Code at the
destination is interpreted as ARM code.
label
is a program-relative expression. See Register-relative and
program-relative expressions on page 3-23 for more information.
BLX label
always causes a change to ARM state.
Usage
The
BLX
instruction:
• copies the address of the next instruction into r14 (lr, the link register)
• causes a branch to
label
, or to the address held in
Rm
• changes instruction set to ARM if either:
— bit 0 of
Rm
is clear
— the
BLX label
form is used.
The machine-level instruction cannot branch to an address outside ±4Mb of the current
instruction. When necessary, the ARM linker inserts code (a veneer) to allow longer
branches (see The ARM linker chapter in ADS Linker and Utilities Guide).
Architectures
This instruction is available in all T variants of ARM architecture version 5 and above.
Examples
BLX r6
BLX armsub