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ARM Instruction Reference
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 4-29
ADDS r4,r0,r2 ; adding the least significant words
ADC r5,r1,r3 ; adding the most significant words
These instructions subtract one 96-bit integer from another:
SUBS r3,r6,r9
SBCS r4,r7,r10
SBC r5,r8,r11
For clarity, the above examples use consecutive registers for multiword values. There is
no requirement to do this. The following, for example, is perfectly valid:
SUBS r6,r6,r9
SBCS r9,r2,r1
SBC r2,r8,r11