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ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 7-51
Examples
AREA cacheable, CODE, ALIGN=3
rout1 ; code ; aligned on 8-byte boundary
; code
MOV pc,lr ; aligned only on 4-byte boundary
ALIGN 8 ; now aligned on 8-byte boundary
rout2 ; code
AREA OffsetExample, CODE
DCB 1 ; This example places the two
ALIGN 4,3 ; bytes in the first and fourth
DCB 1 ; bytes of the same word.
AREA Example, CODE, READONLY
start LDR r6,=label1
; code
MOV pc,lr
label1 DCB 1 ; pc now misaligned
ALIGN ; ensures that subroutine1 addresses
subroutine1 ; the following instruction.
MOV r5,#0x5