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ARM Instruction Reference
4-30 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
4.3.3 AND, ORR, EOR, and BIC
Logical AND, OR, Exclusive OR and Bit Clear.
Syntax
op{cond}{S} Rd, Rn, Operand2
where:
op
is one of
AND
,
ORR
,
EOR
, or
BIC
.
cond
is an optional condition code (see Conditional execution on page 4-4).
S
is an optional suffix. If
S
is specified, the condition code flags are updated
on the result of the operation (see Conditional execution on page 4-4).
Rd
is the ARM register for the result.
Rn
is the ARM register holding the first operand.
Operand2
is a flexible second operand. See Flexible second operand on page 4-24
for details of the options.
Usage
The
AND
,
EOR
, and
ORR
instructions perform bitwise AND, Exclusive OR, and OR
operations on the values in
Rn
and
Operand2
.
The
BIC
(BIt Clear) instruction performs an AND operation on the bits in
Rn
with the
complements of the corresponding bits in the value of
Operand2
.
In certain circumstances, the assembler can substitute
BIC
for
AND
, or
AND
for
BIC
. Be
aware of this when reading disassembly listings. See Instruction substitution on
page 4-26 for details.
Condition flags
If
S
is specified, these instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of
Operand2
(see Flexible second
operand on page 4-24)
• do not affect the V flag.