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ARM Instruction Reference
4-78 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
4.9 ARM pseudo-instructions
The ARM assembler supports a number of pseudo-instructions that are translated into
the appropriate combination of ARM or Thumb instructions at assembly time.
The pseudo-instructions available in ARM state are described in the following sections:
• ADR ARM pseudo-instruction on page 4-79
Load a program-relative or register-relative address (short range)
• ADRL ARM pseudo-instruction on page 4-80
Load a program-relative or register-relative address into a register (medium
range)
• LDR ARM pseudo-instruction on page 4-82
Load a register with a 32-bit constant value or an address (unlimited range)
• NOP ARM pseudo-instruction on page 4-84
NOP
generates the preferred ARM no-operation code.