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ARM Instruction Reference
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 4-27
4.3.2 ADD, SUB, RSB, ADC, SBC, and RSC
Add, subtract, and reverse subtract, each with or without carry.
Syntax
op{cond}{S} Rd, Rn, Operand2
where:
op
is one of
ADD
,
SUB
,
RSB
,
ADC
,
SBC
, or
RSC
.
cond
is an optional condition code (see Conditional execution on page 4-4).
S
is an optional suffix. If
S
is specified, the condition code flags are updated
on the result of the operation (see Conditional execution on page 4-4).
Rd
is the ARM register for the result.
Rn
is the ARM register holding the first operand.
Operand2
is a flexible second operand. See Flexible second operand on page 4-24
for details of the options.
Usage
The
ADD
instruction adds the values in
Rn
and
Operand2
.
The
SUB
instruction subtracts the value of
Operand2
from the value in
Rn
.
The
RSB
(Reverse SuBtract) instruction subtracts the value in
Rn
from the value of
Operand2
. This is useful because of the wide range of options for
Operand2
.
ADC
,
SBC
, and
RSC
are used to synthesize multiword arithmetic (see Multiword arithmetic
examples on page 4-28).
The
ADC
(ADd with Carry) instruction adds the values in
Rn
and
Operand2
, together with
the carry flag.
The
SBC
(SuBtract with Carry) instruction subtracts the value of
Operand2
from the value
in
Rn
. If the carry flag is clear, the result is reduced by one.
The
RSC
(Reverse Subtract with Carry) instruction subtracts the value in
Rn
from the
value of
Operand2
. If the carry flag is clear, the result is reduced by one.
In certain circumstances, the assembler can substitute one instruction for another. Be
aware of this when reading disassembly listings. See Instruction substitution on
page 4-26 for details.