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ARM Instruction Reference
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 4-65
4.7.3 MRC, MRC2
Move to ARM register from coprocessor. Depending on the coprocessor, you might be
able to specify various operations in addition.
Syntax
MRC{cond} coproc, opcode1, Rd, CRn, CRm{, opcode2}
MRC2 coproc, opcode1, Rd, CRn, CRm{, opcode2}
where:
cond
is an optional condition code (see Conditional execution on page 4-4).
coproc
is the name of the coprocessor the instruction is for. The standard name
is
pn
, where
n
is an integer in the range 0-15.
opcode1
is a coprocessor-specific opcode.
Rd
is the ARM destination register. If
Rd
is r15, only the flags field is
affected.
CRn, CRm
are coprocessor registers.
opcode2
is an optional coprocessor-specific opcode.
Usage
The use of these instructions depends on the coprocessor. See the coprocessor
documentation for details.
Note
MRC2
is always unconditional.
Architectures
MRC
is available in ARM architecture versions 2 and above.
MRC2
is available in ARM architecture versions 5 and above.