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Writing ARM and Thumb Assembly Language
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 2-5
In User mode, r14 is used as a link register (lr) to store the return address when a
subroutine call is made. It can also be used as a general-purpose register if the return
address is stored on the stack.
In the exception handling modes, r14 holds the return address for the exception, or a
subroutine return address if subroutine calls are executed within an exception. r14 can
be used as a general-purpose register if the return address is stored on the stack.
The program counter (pc)
The program counter is accessed as r15 (or pc). It is incremented by one word (four
bytes) for each instruction in ARM state, or by two bytes in Thumb state. Branch
instructions load the destination address into the program counter. You can also load the
program counter directly using data operation instructions. For example, to return from
a subroutine, you can copy the link register into the program counter using:
MOV pc,lr
During execution, r15 does not contain the address of the currently executing
instruction. The address of the currently executing instruction is typically pc–8 for
ARM, or pc–4 for Thumb.
The Current Program Status Register (CPSR)
The CPSR holds:
• copies of the Arithmetic Logic Unit (ALU) status flags
• the current processor mode
• interrupt disable flags.
The ALU status flags in the CPSR are used to determine whether conditional
instructions are executed or not. Refer to Conditional execution on page 2-20 for more
information.
On Thumb-capable processors, the CPSR also holds the current processor state (ARM
or Thumb).
On ARM architecture v5TE, the CPSR also holds the Q flag (see The ALU status flags
on page 2-20).
Five Saved Program Status Registers (SPSRs)
The SPSRs are used to store the CPSR when an exception is taken. One SPSR is
accessible in each of the exception-handling modes. User mode and System mode do
not have an SPSR because they are not exception handling modes. Refer to the
Handling Processor Exceptions chapter in ADS Developer Guide for more information.