Filter
Top Products
Vector Floating-point Programming
ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 6-11
bits[18:16]
LEN
is the number of registers used by each vector (see Vec tors on
page 6-6). It is 1 + the value of bits[18:16]:
0b000
LEN
= 1
.
.
0b111
LEN
= 8.
bits[12:8] are the exception trap enable bits:
IXE inexact exception enable
UFE underflow exception enable
OFE overflow exception enable
DZE division by zero exception enable
IOE invalid operation exception enable.
This Guide does not cover the use of floating-point exception trapping.
For information see the technical reference manual for the VFP
coprocessor you are using.
bits[4:0] are the cumulative exception bits:
IXC inexact exception
UFC underflow exception
OFC overflow exception
DZC division by zero exception
IOC invalid operation exception.
Cumulative exception bits are set when the corresponding exception
occurs. They remain set until you clear them by writing directly to the
FPSCR
.
all other bits are unused in the basic VFP specification. They can be used in particular
implementations (see the technical reference manual for the VFP
coprocessor you are using). Do not modify these bits except in
accordance with any use in a particular implementation.
To alter some bits without affecting other bits, use a read-modify-write procedure (see
Modifying individual bits of a VFP system register on page 6-12).