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ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 5-25
Register-controlled shift
These instructions take the value from
Rd
, apply the shift to it, and place the result back
into
Rd
.
Only the least significant byte of
Rs
is used for the shift value.
For all these instructions except
ROR
:
• if the shift is 32,
Rd
is cleared, and the last bit shifted out remains in the C flag
• if the shift is greater than 32,
Rd
and the C flag are cleared.
Immediate shift
These instructions take the value from
Rm
, apply the shift to it, and place the result into
Rd
.
Condition flags
These instructions update the N and Z flags according to the result. The V flag is not
affected.
The C flag:
• is unaffected if the shift value is zero
• otherwise, contains the last bit shifted out of the source register.
Architectures
These instructions are available in all T variants of the ARM architecture.
Examples
ASR r3,r5
LSR r0,r2,#6
LSR r5,r5,av ; av must evaluate, at assembly time, to an
; integer in the range 1-32.
LSL r0,r4,#0 ; same as MOV r0,r4 except that C and V
; flags are not affected
Incorrect examples
ROR r2,r7,#3 ; ROR cannot use immediate shift value
LSL r9,r1 ; high registers not allowed
LSL r0,r7,#32 ; immediate shift out of range
ASR r0,r7,#0 ; immediate shift out of range