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ARM DUI 0068B Copyright © 2000, 2001 ARM Limited. All rights reserved. 5-5
5.1.1 LDR and STR, immediate offset
Load Register and Store Register. Address in memory specified as an immediate offset
from a value in a register.
Syntax
op Rd, [Rn, #immed_5x4]
opH Rd, [Rn, #immed_5x2]
opB Rd, [Rn, #immed_5x1]
where:
op
is either:
LDR
Load register
STR
Store register.
H
is a parameter specifying an unsigned halfword transfer.
B
is a parameter specifying an unsigned byte transfer.
Rd
is the register to be loaded or stored.
Rd
must be in the range
r0
-
r7
.
Rn
is the register containing the base address.
Rn
must be in the range
r0
-
r7
.
immed_5xN
is the offset. It is an expression evaluating (at assembly time) to a multiple
of N in the range 0-31N.
Usage
STR
instructions store a word, halfword, or byte to memory.
LDR
instructions load a word, halfword, or byte from memory.
The address is found by adding the offset to the base address from
Rn
.
Immediate offset halfword and byte loads are unsigned. The data is loaded into the least
significant word or byte of
Rd
, and the rest of
Rd
is filled with zeroes.