Filter
Top Products
20 Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Technical Product Specification
Features Overview
2.2.3.1 Memory Ordering Rule for the MCH
Platforms based on the E7501 chipset require DDR DIMMs to be populated in matched pairs in a
specific order. Start with the two DIMMs furthest from the MCH in a “fill-farthest” approach (see
Figure 2). This requirement is based on the signal integrity requirements of the DDR interface.
2.2.4 I/O
2.2.4.1 Super I/O (U28)
The Super I/O device (SIO) is an SMSC LPC47B272 enhanced Super I/O controller. The SIO
connects to the ICH3 through its LPC bus connection. The SIO provides support for the front panel
serial port (J17, see page 70). There is no front-panel connection to the legacy keyboard and mouse
PS/2 ports. Keyboard and mouse support are provided by the USB connection (J12, see page 77).
See Figure 13 for connector locations.
Figure 2. Memory Ordering
B0894-01
Fill
Last
MCH, U22
Fill
First
J10
J11
J8
J9