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Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer 57
Technical Product Specification
Hardware Management Overview
3.12.1 Reset Logic
The following topics describe the two types of reset requests and the boot relationships among
them. The two types of reset requests available on the MPCBL0001 are:
• Hard reset request (always results in a cold boot)
• Soft reset request (can result in either a warm or cold boot)
A hard reset request occurs whenever the processor Reset line is asserted and then deasserted. A
soft reset occurs whenever an assertion occurs on the processor Init line. Whenever a soft reset
request occurs, the BIOS checks two memory locations to determine whether to initiate a warm
boot while leaving main memory intact or a cold boot that clears memory.
Whenever the BIOS detects that the reset is either a hard reset or a cold boot, it specifically clears
the memory location 40h:72h so it does not contain a 1234h. Under warm boot conditions, this
memory location contains a 1234h (the developer’s application writes this value in this location
[using /dev/mem] when it is started). If a hard reset occurs (as defined in the hard reset topic
below), it is certain that the 40h:72h location contains a non-1234h value.
3.12.2 Hard Reset Request
A Hard Reset, or CPU Reset, is defined as the assertion of the processor reset signal (see Table 24,
“Reset Request” on page 58). This initializes the processor state and registers, disables internal
caches, and causes the processor to unconditionally begin execution from the reset vector. A hard
reset is initiated by the following events:
1. A power up of the SBC. The SMC enables the onboard power supplies.
2. The SMC negates the ICH3_PWROK signal (see Note below).
3. A “reset” command from the Port CF9h I/O register (refer to the “Intel
®
82801CA I/O
Controller Hub 3 (ICH3-S) Datasheet” for information about this register).
4. Watchdog timer (WDT #1) expires and is configured to initiate a hard reset. See “Watchdog
Timers (WDTs)” on page 62 for more information.
5. Watchdog timer (WDT #3) expires after failure to perform the first instruction fetch.
6. A command (cmmset -l bladex -d powerstate -v reset) is issued from MPCMM0001.
Note: The IPMC can negate the dedicated signal ICH3_PWROK to initiate a processor reset.
ICH3_PWROK indicates whether power is OK. If the IPMC deasserts ICH3_PWROK, the
hardware asserts the processor reset lines.
3.12.3 Soft Reset Request
The assertion of the processor’s INIT signal causes a soft reset or “CPU INIT” (see Table 24,
“Reset Request” on page 58). The ICH3 is normally responsible for driving the INIT signal. A
CPU INIT event causes the processor(s) to fetch the reset vector at the next instruction boundary.
The majority of the processor and all of the cache states are unaffected by an INIT event.
After the INIT event, hardware may be reset (or not reset) under BIOS control. PCI buses are reset
using their respective bridge control registers. This signal is then level translated to the processor
compatible signal level. INIT may be caused by the following events: