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Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer 41
Technical Product Specification
Hardware Management Overview
3.2.6 System ACPI Power State
MPCBL0001 is targeted to support ACPI functionality, with support for the sleep states S0, S4 &
S5. On assertion of ICH3_SLP_S5# and ICH3_SLP_S3# GPIOs, IPMC sends out a hot-swap event
message to the shelf manager requesting deactivation. On successful reception of a deactivation
message from the shelf manager, the FRU enters M1 power state and remains in this state.
Under conditions where an ACPI enabled operating system is in S4/S5 sleep state, the chipset
could deassert ICH3_SLP_S5# and ICH3_SLP_S3# GPIOs requiring the IPMC to attempt
AdvancedTCA power state transition to M4 state (through M2, M3).
ACPI capabilities of an operating system are communicated by BIOS to the IPMC at initialization.
An OEM style IPMI command is sent by BIOS for this purpose. This command (SetACPIConfig ;
NetFn: 30h, command: 83h) is sent by BIOS every time an operating system is initialized. The
IPMC firmware defaults to no ACPI until this command is received with proper data in the request
to indicate the OS is either ACPI enabled or disabled. For obvious reasons, this command is only
executable over SMS channel.
3.2.7 IPMB Link Sensor
The MPCBL0001 provides two IPMB links to increase communication reliability to the shelf
manager and other IPM devices on the IPMB bus. These IPMB links work together for increased
throughput where both busses are actively used for communication at any point. A request might
be received over IPMB Bus A, and the response is sent over IPMB Bus B. Any requests that time
out are retried on the redundant IPMB bus. In the event of any link state changes, the events are
written to the MPCBL0001 SEL. IPMC monitors the bus for any link failure and isolates itself
from the bus if it detects that it is causing errors on the bus. Events are sent to signify the failure of
a bus or, conversely, the recovery of a bus.
3.2.8 FRU Hot Swap
The hot-swap event message conveys the current state of the FRU, the previous state, and a cause
of the state change as can be determined by the IPMC. Refer to PICMG 3.0 Specifications for
further details on the hot-swap state.
3.2.9 CPU Failure Detection
A CPU failure during runtime or POST will have better error handling: a SEL event notification
will be generated if either one of the CPUs fails to power up, and the Health LED will turn red.
1. An FRB3 timer (30 seconds) was implemented to detect the failure of the CPUs to boot. This
also now implements offset 04h in the CPU 0 Status sensor. When asserted, it will generate an
event and set the Health LED to red.
2. The SMI line is now checked for a long (10 second) assertion that indicates a severe hardware
failure around the CPUs during runtime. As a result, a new discrete sensor has been added
(SMI Timeout) that will assert when the SMI line stays asserted too long.
Refer to Table 9 for the SEL events associated with FRB3 timer timeout and SMI Timeout
assertion.