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Programming Considerations Chapter 5
GPIB-1014 User Manual 5-8 © National Instruments Corporation
6. When the Valid auxiliary command is issued, the TLC assumes that the My Secondary
Address (MSA) message has been received, which causes the following events to occur:
• The LA bit to be set and the TA bit to be cleared (LADS=TIDS=1) if LPAS was set, or
the TA bit to be set and the LA bit to be cleared (TADS=LIDS=1) if TPAS was set.
• The GPIB DAC message to be sent true, and the GPIB handshake to be finished.
7. When the Non-Valid auxiliary command is issued, the TLC assumes that the Other
Secondary Address (OSA) message has been received, which causes the following events to
occur:
• The TLC Talker or Listener function to go to its idle state (TIDS=1 or LIDS=1) if the
either the TPAS or LPAS bit was set.
• The GPIB DAC message to be sent true, and the handshake to be finished.
Until a GPIB Primary Command Group (PCG) message is received (that is, as long as the
subsequent messages are secondary addresses), the APT bit is set and a DAC holdoff is in effect
each time a GPIB secondary address is received. In this way, the GPIB CIC can address several
devices having the same primary address without repeating the primary address each time. If a
PCG message is received before a secondary address is received, the TPAS and LPAS bits are
cleared.
Sending/Receiving Messages
When the TLC is a GPIB Talker or Listener, data (device-dependent messages) can be sent or
received using either DMA or programmed I/O. When the TLC is Active Controller, commands
(remote multiline messages) can be sent using programmed I/O only. The default configuration
is programmed I/O (DMA mode is activated only by issuing a specific sequence of commands to
the GPIB-1014). In either programmed I/O or DMA modes, the GPIB interface functions are
programmed or addressed in the same way, with minor exceptions described in the next section.
Using Direct Memory Access
The onboard DMA Controller is the 68450 (DMAC). This chip provides four independent DMA
channels, of which two channels (Channel 0 and 1) can be used by the GPIB-1014 to transfer
data between the VMEbus memory and the GPIB. The GPIB-1014 supports single-address
(flyby mode) DMA transfer to/from the TLC where data bytes transfer directly between VMEbus
memory and the TLC.
Although the 68450 supports several different DMA request generation modes, it must be
programmed for external, cycle steal DMA request, since the TLC asserts the DMA request line
before each transfer. The DMAC can be programmed via the REQG bits in the OCR to perform
cycle steal with hold or cycle steal without hold mode transfers.