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Theory of Operation Chapter 6
GPIB-1014 User Manual 6-20 © National Instruments Corporation
address the device (VMEbus memory) in dual-address transfers. It is initiated before starting the
channel operation. The BAR is used only in chaining or continue operations.
Transfer Count Register Operation. The DMAC has two 16-bit transfer counter registers per
channel: the Memory Transfer Counter (MTCR) and the Base Transfer Counter (BTCR). The
MTCR is used in all operations to count the number of operands transferred in a block. It is
decremented by one after each operand is transferred. This register is either initialized before the
channel operation is started or is loaded during chaining or continue operations. The BTCR is
used for chaining and continue operations. Both the MTCR and the BTCR have a terminal count
of zero. If either register is initialized or loaded with a terminal count when the channel is
configured to use that register, a count error is signaled.
Initiation and Control of Channel Operation
The Channel Control Register (CCR) provides mechanisms for starting, continuing, halting, or
aborting an operation. It also controls the enabling of interrupts from a channel.
Initiating the Operation. To initiate the operation of a channel, the STR bit of the CCR is set to
start the operation. Setting the STR bit causes the immediate activation of the channel. The
channel is ready to accept requests immediately. In the GPIB applications, the DMAC is ready
to accept DMA requests from the TLC. The channel initiates the operation by first clearing the
STR bit and then setting the channel active (ACT) bit in the CSR. Any pending requests are
cleared and the channel is then ready to receive requests for the new operation. If the channel is
configured for an illegal operation, the configuration error is signaled and no channel operation is
run. Illegal operations include selecting any of the operations marked undefined, reserved. If the
DMA operation is dual-address (for memory-to-memory DMA), the DAR must have been
previously initialized. The channel cannot be started if any of the ACT, COC, BTC, NDT, or
ERR bits is set in the CSR. In this case, the channel signals an operation timing error.
If the operation is unchained, as to transfer a single block of data, the MAR and the MTCR
should have been previously initialized. If the operation is chained, as to transfer multiple blocks
of data, the BAR and/or the BTCR should have been previously initialized. For array-chained
operation, both the BAR and BTCR should have been previously initialized. For linked chained
operation, only the BAR is to be initialized.
The Continue Mode of Operation. The continue bit (CNT) can transfer multiple blocks in
unchained operations. The CNT bit is set to continue the current channel operation. If an
attempt is made to continue a chained operation, a configuration error is signaled. The BAR and
BTCR should have been previously initialized. The continue bit can be set at the same time as
the STR bit is set (to start a channel) or it can be set while the channel is still active. The
operation timing error bit is signaled if a continuation is otherwise attempted. GPIB-1014
applications generally do not use the continue mode of operation.
Halt. The CCR has a halt bit that can suspend the operation of the channel. If this bit is set, a
request can still be generated and recognized, but the DMAC does not attempt to acquire the bus