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Register Descriptions Chapter 4
GPIB-1014 User Manual 4-40 © National Instruments Corporation
Bit Mnemonic Description
2w TRI Three-State Timing Bit
The TRI bit determines the TLC GPIB Source Handshake Timing, T1.
TRI can be set to enable high-speed data transfers (T1 ≥ 500 nsec)
when tri-state GPIB drivers are used. (The GPIB-1014D uses tri-state
GPIB drivers except during Parallel Poll responses, in which case the
GPIB drivers automatically switch to Open Collector.) Setting TRI
enables high-speed timing as T1 of the GPIB Source Handshake after
transmission of the first byte. Clearing TRI sets the low-speed timing
(T1 ≥ 2 µsec).
1w SPEOI Send Serial Poll EOI Bit
The SPEOI bit permits or prohibits the transmission of the END
message in Serial Poll Active State (SPAS). If SPEOI is set, EOI is
sent true when the TLC is in SPAS; otherwise, EOI is sent false in
SPAS.
0w CPT ENABLE Command Pass Through Enable Bit
The CPT ENABLE bit permits or prohibits the detection of undefined
GPIB commands and permits or prohibits the setting of the CPT bit
(ISR1[7]r) on receipt of an undefined command. When CPT
ENABLE is set and an undefined command has been received, the
DAC message is held and the Handshake stops until the Valid
auxiliary command is issued. The undefined command can be read
from the CPTR and processed by the software.