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Chapter 4 Register Descriptions
© National Instruments Corporation 4-53 GPIB-1014 User Manual
Operation Control Register
VMEbus Address: Base Address + 05 (hex)
Attributes: Read/Write, Internal to DMAC
7 654 3210
DIR
0 SIZE CHN REQG R/W
The Operation Control Register (OCR) is an operation-oriented register.
Bit Mnemonic Description
7r/w DIR Direction Bit
The Direction bit specifies the direction of the transfer, to or from
VMEbus memory :
0 = Transfer from memory to device
1 = Transfer from device to memory
In GPIB applications, 0 indicates transfers from memory to GPIB and
1 indicates transfers from GPIB to memory.
6r/w 0 Reserved Bit
Write zero to this bit.
5-4r/w SIZE Size Bits 5 through 4
The Size bits indicate the size of the data transfer. For the GPIB-1014
GPIB transfers, the size is always byte 00. For memory-to-memory
transfers, the size can be byte, word, or long-word.
00 = Byte (8 bits)
01 = Word (16 bits)
10 = Long-word (32 bits)
11 = (undefined, reserved)
3-2r/w CHN Chain Bits 3 through 2
The Chain bits are used to indicate what type of chaining, if any, is
used:
00 = Chain operation is disabled
01 = (undefined, reserved)