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Bit Mnemonic Description
ERR IE: Enable Interrupt on Error Bit
END RX: End Received Bit
END IE: Enable Interrupt on End Received Bit
DEC: Device Clear Bit
DEC IE: Enable Interrupt on Device Clear Bit
DO: Data Out Bit
DO IE: Enable Interrupt on Data Out Bit
DI: Data In Bit
DI IE: Enable Interrupt on Data In Bit
SRQI: Service Request Input Bit
SRQI IE: Enable Interrupt on Service Request Input Bit
REMC: Remote Change Bit
REMC IE: Enable Interrupt on Remote Change Bit
CO: Command Output Bit
CO IE: Enable Interrupt on Command Output Bit
LOKC: Lockout Change Bit
LOKC IE: Enable Interrupt on Lockout Change Bit
ADSC: Address Status Change Bit
ADSC IE: Enable Interrupt on Address Status Change Bit
7w 0 Reserved Bit
Write zero to this bit.
6r SRQI Service Request Input Bit
6w SRQI IE Service Request Input Interrupt Enable Bit
SRQI is set when:
(CIC & SRQ & -(RQS & DAV)) becomes true or (CIC & SRQ &
RQS & DAV) becomes true.
SRQI is cleared by:
pon + (read ISR2)
Notes
CIC: GPIB Controller-In-Charge
SRQ: GPIB Service Request message
RQS: GPIB Request Service message
DAV: GPIB Data Valid message
pon: Power On Reset
read ISR2: Bit is cleared immediately after it is read
The SRQI bit indicates that a GPIB Service Request (SRQ) message
has been received while the TLC function is active (CIC=1).
Note: The set SRQI equation only applies to situations in which two
or more devices are issuing the SRQ message.