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Chapter 5 Programming Considerations
© National Instruments Corporation 5-21 GPIB-1014 User Manual
Interrupts
If the GPIB-1014 is enabled for interrupts, there are three events that can cause an interrupt on
the VMEbus. The first event is an interrupt from the TLC. The second event is a GPIB
handshake synchronization that occurs when a DMA transfer is finished and the GPIB is
synchronized. The last event is a bus error that occurs during a DMA transfer. Interrupts must
be enabled in software to be recognized as described in the following paragraphs.
The Interrupter circuitry of the GPIB-1014 enables the board to interrupt the CPU to request
service. The hardware offers programmable selection of the interrupt priority level (level 1 to
level 7) via Configuration Register 1. Interrupts can be generated on numerous conditions.
These conditions can also be detected by polling if desired. If interrupts are enabled, the
GPIB-1014 generates an interrupt on any of the following conditions:
• An interrupt request is received from the GPIB TLC.
• A bus error occurs during a DMA transfer.
• A DMA transfer from memory to the GPIB is complete and the GPIB is synchronized (that
is, all devices have accepted the last byte).
or
A DMA transfer from the GPIB to memory is complete and the GPIB is synchronized.
All interrupt sources from the GPIB-1014 are routed to the onboard DMAC, which actually
generates the interrupt request on the VMEbus. The Peripheral Control Line (PCL1) of Channel
1 is used as a status input for the interrupt sources listed earlier. These events are ORed together
so that a transition on the PCL1 occurs when any of these events occur. If programmed as a
status input, the status level of the PCL can be determined by reading the PCS bit in the CSR. If
a negative transition occurs on this input, the PCT bit of the CSR is automatically set. Any of the
four DMAC channels can be programmed to generate an interrupt on a negative transition (high
to low) on its PCL. This enables an interrupt, which is requested when the PCT bit of the CSR is
set, indicating that a transition has occurred.