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Chapter 4 Register Descriptions
© National Instruments Corporation 4-55 GPIB-1014 User Manual
Sequence Control Register
VMEbus Address: Base Address + 06 (hex)
Attributes: Read/Write, Internal to DMAC
7 654 3210
0 0 0 0 MAC DAC R/W
The Sequence Control Register (SCR) is used to define the sequencing of memory and device
addresses.
Bit Mnemonic Description
7-4r/w 0 Reserved Bits
Write zeros to these bits.
3-2r/w MAC Memory Address Count Bits 3 through 2
The Memory Address Count bits indicate the count sequence of the
Memory Address Register:
00 = Memory address does not count
01 = Memory address register counts up
10 = Memory address register counts down
11 = (undefined, reserved)
1-0r/w DAC Device Address Count Bits 1 through 0
The Device Address Count bits indicate the address sequence of the
Device Address Register. This is only used in flowthrough
memory-to-memory DMA transfers.
00 = Device address does not count
01 = Device address register counts up
10 = Device address register counts down
11 = (undefined, reserved)