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Chapter 5 Programming Considerations
© National Instruments Corporation 5-17 GPIB-1014 User Manual
4. Once channels 0 and 1 have been configured properly, start the DMA channels. Start
Channel 1 before starting Channel 0. The channels are started by writing to the CCRs with
the STR bits set. (Channel 1 should also have the EINT bit set if you are using interrupts.)
5. Finally, configure the TLC for a DMA operation. The sequence is as follows:
a. Set the END IE bit in IMR1 if the TLC is a GPIB Listener. Set the ERR IE bit in IMR1
if the TLC is a GPIB Talker.
b. Set the DMAO bit in IMR2 if the TLC is a GPIB Talker. Otherwise, clear DMAO.
c. Set the DMAI bit in IMR2 if the TLC is a GPIB Listener. Otherwise, clear DMAI.
Polling During DMAs
All the GPIB-1014 registers are accessible during DMA operations while the CPU has control of
the bus. If interrupts are not enabled, the CSR of Channel 1 can be read to check that the PCT bit
is set.
Sending END or EOS
To send the GPIB END message with the last data byte, use the carry cycle feature as described
in the DMA Transfers With A Carry Cycle section earlier in this chapter.
Terminating the Transfer and Checking the Result
If either Channel 0 or 1 is improperly programmed, the ERR bit in the CSR of the active channel
is set by the DMAC and the CER of the channel indicates a configuration error. The following
paragraphs assume the channels are properly programmed to allow normal termination of a GPIB
DMA transfer. They describe how to check the CSR of the channel to determine the success of
the GPIB DMA transfers.
The termination of the GPIB DMA transfer causes an interrupt if interrupts have been enabled in
Channel 1. If interrupts are not used, this condition can be detected by polling. Regardless of
whether or not the carry cycle feature is used, when the DMA transfer is complete (that is, all
data blocks have been transferred) and the GPIB is synchronized (that is, all Listeners have
accepted the last byte), a transition occurs on the Channel 1 PCL line of the DMAC. The PCT
bit in the CSR of Channel 1 is set by this transition. This generates an interrupt if Channel 1 is
configured to interrupt on a PCL transition. This transition can also be detected by polling the
CSR of Channel 1 and waiting for the PCT bit to set. Once detected, the software must service
the interrupt condition.
The first action in the interrupt handler must be determining what caused the interrupt. A
VMEbus interrupt can be caused by any of the following events: