Filter
Top Products
Programming Considerations Chapter 5
GPIB-1014 User Manual 5-10 © National Instruments Corporation
DMA Transfers without the Carry Cycle
Data
Block
A
Total = N bytes
NO CHAINING
OR
Total = N bytes
Data
Block A
Data
Block B
Data
Block C
CHAINING
DMAC
VMEbus
interrupt
TLC interrupt
Bus Error
GPIB Sync.
PCL1
Channel 0
Figure 5-1. DMA Transfer without Carry Cycle
If the carry cycle feature is not needed in a transfer sequence, little programming is needed.
Channel 0 is used to transfer the entire block of data, since the carry cycle byte does not need to
be inserted before the last data byte. Channel 1 DMA is not used and must not be started. As
indicated in Figure 5-1, depending upon the number of data blocks to be transferred, you can use
no-chaining or chaining mode. If interrupts are enabled on Channel 1, the TLC can interrupt the
processor on the VMEbus system on one of 13 GPIB events. Similarly, if BERR* occurs during
a DMA transfer, the processor is also interrupted. When the GPIB handshake is synchronized,
the system is also interrupted and you can check the COC and ERR bit in the CSR of Channel 0
to determine the status of the DMA transfer. This is described further in Terminating the
Transfer and Checking the Result later in this chapter.
A detailed programming sequence for DMA transfers without a carry cycle is as follows:
1. In CFG1, the CC bit must be cleared to 0. The DIR bit should be set to reflect the direction
of the DMA transfer (1=GPIB-to-Memory, 0=Memory-to-GPIB). The ROR* bit must also
be set if the Release On Request feature is to be enabled. If interrupts are used, the INTRQ
bits are set to select the interrupt level. BRG bits must be set to choose one of four VMEbus
request lines.
2. Channel 0 must be configured to provide a flyby transfer for the n data bytes between the
GPIB and the VME system memory. The sequence is as follows:
a. The CCR of Channel 0 must be written with the SAB bit set to abort the channel
operation in case it is still active.