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Chapter 2 Powering On and Configuring BIOS Settings 2-9
Chipset
Configuration
Caution: Do not
change the
settings unless
you are sure of
what you are
doing. Setting
items on this
menu to
incorrect values
may cause your
system to
malfunction.
Options for advanced chipset features. Options include:
• SRAT Table: Enables the ACPI 2.0 Static Resource
Affinity Table for OSs that support an SRAT and will
disable node interleaving. Disabled allows for node
interleaving. Options include: Enabled and Disabled.
Enabled
• Node Interleave: If set to Auto, node interleaving will be
enabled if memory sizes match, SRAT table is disabled
and if DRAM ECC scrubbing is disabled. Options
include: Auto and Disabled.
Disabled
• Bank Interleave: If set to Auto, bank interleaving is
enabled if the memory size and type match. Options
include: Auto and Disabled.
Auto
• ECC: Enable or disable ECC check/correct mode. This is
a global enable function for all blocks within the CPU
core and North Bridge.
Enabled
• DRAM ECC: If all memory in the system supports ECC
(x72), enabling invokes initial scrub DRAM and enables
system requests to DRAM to be checked and/or
corrected. Options include: Enabled and Disabled.
Enabled
• ECC Scrub Redirection: Enable or disable ECC Scrubber
to correct errors detected in DRAM during normal CPU
requests (foreground scrubbing).
Enabled
• Chip-Kill: Enabled or disable the ChipKill ECC on nodes
with all x4 ECC capable DIMMS.
Enabled
• DCACHE ECC Scrub CTL: Sets the rate of background
scrubbing for DCACHE lines. Options include: 5.12 µs,
10.2 µs, 20.5 µs, 41.0 µs, Disabled, 640 ns, 1.28 µs, 2.56 µs.
5.12 µs
• L2 ECC Scrub CTL: Sets the rate of background
scrubbing for L2 cache lines. Options include: 10.2 µs,
20.5 µs, 41.0 µs, 81.9 µs, Disabled, 1.28 µs, 2.56 µs,
5.12 µs.
10.2 µs
• DRAM ECC Scrub CTL: Sets the rate of background
scrubbing for DRAM (in addition to normal ECC
scrubbing from system requests). Background agent
works independently of CPU requests and bus masters,
but cannot be enabled without first enabling DRAM
ECC. Options include: 163.8 µs, 327.7 µs, 655.4 µs, 1.31
ms, Disabled, 20.5 µs, 41.0 µ
s, 81.9 µs.
163.8 µs
• No Spec. TLB Reload: When this is at the default
(Disabled), the translation look-aside buffer (TLB) is
reloaded. When enabled, TLB reloading is turned off.
Disabled
TABLE 2-3 BIOS Advanced Menu (Continued)
Menu Option Description Default